Join us in reinventing the future of general-purpose computing
Ascenium is seeking experienced team members eager to contribute to the development of something truly exceptional – a processor creation effort unlike any other.
About Ascenium and Our Approach
Ascenium is a Norwegian company with engineering teams located in Oslo, Stavanger, and Trondheim. Our company is owned by Norwegian shareholders with a proven track record of disruption in technology markets, and a long perspective.
What We Do
We design the next-generation data center CPU and Processor block, challenging Intel’s x86 architecture and monopoly.
Why We Do It
The global need for a lower CO2 footprint drives our mission. Data centers currently consume energy equivalent to international air traffic – about 200 TWh yearly and increasing.
According to all independent sources, more energy-efficient CPUs are the key solution to significantly reducing CO2 footprint in data centers.
Working at Ascenium
At Ascenium, we believe in hiring exceptional individuals, setting clear priorities, and empowering our team members to thrive. We find that our approach not only makes sense form a business perspective but is also highly valued by our engineers.
Available positions
Open application
You know who you are and understand the skill sets necessary to build a high-performance state-of-the-art microprocessor. Perhaps you’re already familiar with our work through our open-source efforts?
If you are interested in taking part, please don’t hesitate to reach out.
For a virtual coffee, please contact:
Jo Uthus (CEO)
+47 473 80 634
E-mail
Øyvind Harboe (VP Software Engineering)
E-mail
Here’s how we make it work:
Is it Possible?
Is it possible to compete with Intel, you might ask? Yes. Hard? Again, yes. But we believe it’s both achievable and worthwhile. Intel designed the x86 architecture five decades ago and in principle, hasn’t been able to improve the key characteristic of power consumption despite shrinking process nodes and increasing clock frequency in the CPU domain.
Intel achieves its current performance with a massively complex out-of-order CPU architecture that consumes high amounts of energy. New chips do not improve performance, quite the contrary. Other disruptors base their designs on ARM RISC and RISC-V, but they are not materially different from x86. The instruction set doesn’t matter, they are all out-of-order RISC CPUs at the heart.
Data center applications are focused on Integer Performance, which is Ascenium’s focus.
Competencies and Tools
- Compiler development (LLVM)
- RTL, using Chisel
- EDA tooling: synthesis, floorplan, place, route. No detailed power and physical concerns at this point.
- C++ development in the space of LLVM backend, as well as simulation. We prefer the latest compilers, as well as tools like clang-tidy, clang-format, etc.
- Python and various scripting for CI and utilities
- Chisel, a DSL based on Scala that utilizes functional programming concepts as well as procedural programming to generate RTL (Verilog)
- OpenROAD for flushing out major issues in the RTL and having quantitative data-driven feedback
- Open source, extensively. This includes engaging with the community, and we are transitioning to commercial PDK and EDA tools as our technology is maturing
- Google Workspace, GitHub, etc. are also in use.
Core Technology Overview
Designing the new processor and tools, our core technology includes:
- Compiler: LLVM and implementing our own backend
- CPU: Simulation in C++ RTL/Verilog, with a preference for open-source EDA tools during R&D phase
- Benchmarking against industry-standard metrics:
EEMBC CoreMark SPECInt2017 (for data center chips)