Performance

Simple Architecture – Scales with Area

  • Turns user program into a series of large circuits
  • Executes 100 ARM instruction equivalents at a time
  • Loops & pipelining happen in place, automatically
    • Over 90% of time spent in short loops
  • Dozens to hundreds of times faster than existing processors
  • Restores performance growth to processor industry!

Keep Existing Code

  • Any GCC language source code unedited
  • No architecture or instruction set to learn
  • No constraints on coding style
  • Breakthrough performance on a wide variety of applications

Low Power

  • Executes 100 ARM instruction equivalents at a time
  • Eliminates huge amount of memory and register operations
    • Over 90% of power consumption in short loops
  • Compact 10M transistor core
  • Runs at 0.7V at all times

Cost Effective

Compact 10M transistor core

  • Standard CMOS processing
  • Standard packaging or core technology
  • Very efficiently uses only the 8 simple functions needed by the Ascenium compiler

Ease of Use/TTM

Nothing to Learn or Hand Optimize

  • Any GCC language source code unedited
  • No special coding style
  • Automated tools
  • No hand optimization
  • No architecture to learn

Technology

What Makes It Easy to Use?

  • No architecture to learn – No distraction set
  • Existing high-level languages unedited
  • Desired user code changes quick & easy
  • Quick TTM
  • Totally general purpose – not a niche product

What Makes It Faster?

  • Ascenium compiler uses GCC/LLVM output
  • Turns user program into a large circuit
  • Executes ≈16 lines of source code at a time
  • Loops and pipelining happens in place and automatically due to marriage of smart compiler/arch
    • >90% of time spent in loop ??????
  • Dozens to 100s of times faster than existing processors
mooreslaw-big

What Makes It Low Power?

  • Flattening loops and pipe/?? avoids mountains of memory/register operations
    • >90% of power consumption in loops ≤4 lines of codecost-effective

What Makes It Cost Effective?

  • RISC:CISC @Ascenium:RISC
  • Array of ?? very simple logic blocks
    • ≈8 functions
    • Does all the compiler needs
    • Onlly 2K bits to configure entire ??
    • Big enough for vast majoirty of loops, pipeline?? to happen in place