The Ascenium Rocket processor eliminates the performance bottleneck of the classic CPU's deep instruction pipeline that has stalled CPU performance improvements for generations. The Rocket processor has no instruction set. Instead Rocket constructs a succession of hardware circuits in real time that implement the functional intent of the source code. Rocket is a breakthrough general purpose non-Von Neumann architecture that will change the world of computing!

  • a s c e n i u m : A revolutionary compiler that takes a user’s standard C-code, exploits the parallelism in it and turns it into a succession of hardware circuits encoded as configuration words for the Ascenium fabric – delivering exceptional performance at very low power consumption.

Performance

Simple Architecture – Scales with Area

  • Turns user program into a series of customized circuits
  • Executes 100 MIPS assembly instruction equivalents at a time
  • Loops & pipelining happen in place, automatically
    • Over 90% of time spent in short loops
  • Much faster than existing processors

Keep Existing Code

  • Any GCC language source code unedited
  • No architecture or instruction set to learn
  • No constraints on coding style
  • Breakthrough performance on a wide variety of applications

Low Power

  • Executes 100 MIPS instruction equivalents at a time per Rocket machine cycle
  • Eliminates huge amount of memory and register operations
    • Over 90% of power consumption in short loops
  • Compact implementation
  • Exploits spatial advantages to reduce power consumption

Cost Effective

Compact implementation

  • Standard CMOS processing
  • Standard packaging or core technology
  • Homogenous fabric

Ease of Use/TTM

Nothing to Learn or Hand Optimize

  • Any GCC language source code unedited
  • No special coding style
  • Automated tools
  • No hand optimization
  • No architecture to learn

Performance

Simple Architecture – Scales with Area

  • Turns user program into a series of large circuits
  • Executes 100 ARM instruction equivalents at a time
  • Loops & pipelining happen in place, automatically
    • Over 90% of time spent in short loops
  • Dozens to hundreds of times faster than existing processors
  • Restores performance growth to processor industry!

Keep Existing Code

  • Any GCC language source code unedited
  • No architecture or instruction set to learn
  • No constraints on coding style
  • Breakthrough performance on a wide variety of applications

Low Power

  • Executes 100 ARM instruction equivalents at a time
  • Eliminates huge amount of memory and register operations
    • Over 90% of power consumption in short loops
  • Compact 10M transistor core
  • Runs at 0.7V at all times

Cost Effective

Compact 10M transistor core

  • Standard CMOS processing
  • Standard packaging or core technology
  • Very efficiently uses only the 8 simple functions needed by the Ascenium compiler

Ease of Use/TTM

Nothing to Learn or Hand Optimize

  • Any GCC language source code unedited
  • No special coding style
  • Automated tools
  • No hand optimization
  • No architecture to learn