The Ascenium Aptos is the first in a new class of processor type known as a Software Defined Processor (SDP). An SDP is a general purpose processor without an instruction set. The Aptos processor eliminates the performance bottleneck of the classic CPU's deep instruction pipeline that has stalled CPU performance improvements for generations. Aptos is a breakthrough general purpose non-Von Neumann architecture.

  • asenium aptos: Aptos is both a disruptive processor architecture as well as a revolutionary LLVM backend that better exploits the parallelism in a user’s high level code (such as C++). The Aptos architecture continuously physically evolves in space and time under software control to optimally implement the functional intent of the user’s program.

Performance

Simple Architecture – Performance scales with Area

  • Turns user program into a series of customized circuits
  • Executes 100 MIPS assembly instruction equivalents at a time
  • Loops & pipelining happen in place, automatically
    • Over 90% of time spent in short loops
  • Much faster than existing processors

Keep Existing Code

  • Any GCC language source code unedited
  • No architecture or instruction set to learn
  • No constraints on coding style
  • Breakthrough performance on a wide variety of applications

Low Power

  • Executes 100 MIPS instruction equivalents at a time per Rocket machine cycle
  • Eliminates huge amount of memory and register operations
    • Over 90% of power consumption in short loops
  • Compact implementation
  • Exploits spatial advantages to reduce power consumption

Cost Effective

Compact implementation

  • Standard CMOS processing
  • Standard packaging or core technology
  • Homogenous fabric

Ease of Use/TTM

Nothing to Learn or Hand Optimize

  • Any GCC language source code unedited
  • No special coding style
  • Automated tools
  • No hand optimization
  • No architecture to learn

Performance

Simple Architecture – Scales with Area

  • Turns user program into a series of large circuits
  • Executes 100 ARM instruction equivalents at a time
  • Loops & pipelining happen in place, automatically
    • Over 90% of time spent in short loops
  • Dozens to hundreds of times faster than existing processors
  • Restores performance growth to processor industry!

Keep Existing Code

  • Any GCC language source code unedited
  • No architecture or instruction set to learn
  • No constraints on coding style
  • Breakthrough performance on a wide variety of applications

Low Power

  • Executes 100 ARM instruction equivalents at a time
  • Eliminates huge amount of memory and register operations
    • Over 90% of power consumption in short loops
  • Compact 10M transistor core
  • Runs at 0.7V at all times

Cost Effective

Compact 10M transistor core

  • Standard CMOS processing
  • Standard packaging or core technology
  • Very efficiently uses only the 8 simple functions needed by the Ascenium compiler

Ease of Use/TTM

Nothing to Learn or Hand Optimize

  • Any GCC language source code unedited
  • No special coding style
  • Automated tools
  • No hand optimization
  • No architecture to learn