Performance

Simple Architecture – Scales with Area

  • Turns user program into a series of large circuits
  • Executes 100 ARM instruction equivalents at a time
  • Loops & pipelining happen in place, automatically
    • Over 90% of time spent in short loops
  • Dozens to hundreds of times faster than existing processors
  • Restores performance growth to processor industry!

Keep Existing Code

  • Any GCC language source code unedited
  • No architecture or instruction set to learn
  • No constraints on coding style
  • Breakthrough performance on a wide variety of applications

Low Power

  • Executes 100 ARM instruction equivalents at a time
  • Eliminates huge amount of memory and register operations
    • Over 90% of power consumption in short loops
  • Compact 10M transistor core
  • Runs at 0.7V at all times

Cost Effective

Compact 10M transistor core

  • Standard CMOS processing
  • Standard packaging or core technology
  • Very efficiently uses only the 8 simple functions needed by the Ascenium compiler

Ease of Use/TTM

Nothing to Learn or Hand Optimize

  • Any GCC language source code unedited
  • No special coding style
  • Automated tools
  • No hand optimization
  • No architecture to learn

Status

  • Patents
    • 5 issued with good choke points
    • 2 allowed
    • 4 pending
  • Compiler (120K lines of code)
    • Runs DSP benchmarks clean at >10x performance over next best
    • Behavioral simulator runs 35K lines of test code clean
      • Working steadily towards 100K lines
  • Hardware Implemented
    • Xilinx FPGA board
    • 500K lines of verilog
    • Expect to run 50K lines under test code base clean 9/16
  • Ready to run user sample code <20K lines as of 9/16